In recent years, UVPROM where stored contents are erased by ultraviolet rays and EEPROM (electrically erasable and programmable ROM) where stored contents are electrically rewritten using a special instrument have been used widely. EEPROM is facile and convenient since its user can program it electrically, while a conventional ROM, such as mask ROM that contents are built in as a mask when fabricated, employs a structural programming technique. However, its reliability to programming and erasing is generally lower than ROM. Namely, program verify to ensure easily that no output exists after programming by charging electric charge into a floating gate, and erase verify to ensure securely that certain output exists after erasing by discharging electric charge from a floating gate become important matters.
A conventional examples of this kind of non-volatile semiconductor storage device is shown in FIG. 1. This non-volatile semiconductor storage device is EEPROM disclosed in Japanese patent application laid-open No. 5-36288 (1993). The reading output of a memory cell transistor TC00 etc. is led through a Y-gate transistor section B2 to a load transistor section B4, and the reading output of a dummy transistor TRD0 etc. is led through connection part B3 to a dummy load transistor section B5.
The load transistor section B4, the dummy load transistor section B5 and a differential amplifier B6 compose a sense amplifier. The differential amplifier B6 outputs amplifying the different between input IN1 from the load transistor section B4 and IN2 from the dummy load transistor section B5 when power-down signal line PD becomes "L" in its operation. In the dummy load transistor section B5, two dummy load transistors TL1 and TL2 are connected in parallel between power source voltage Vcc and output of dummy transistor TRD0 etc. Therefore, the equivalent resistance value of the dummy load transistors TL1 and TL2 is a half of the equivalent resistance value of a load transistor TL0 on the load transistor section B4 side. Here, since the gates of the memory cell transistor TC00 and dummy transistor TRD0 are connected to a same word line X0, they have same current drive power. Also, since in a gate voltage control circuit B7, a read bar signal line #R is "L", same applies to a reference transistor TR. Therefore, input IN2 outputs an intermediate voltage between when IN1 is reading out "1" and when IN1 is reading out "0", which means that a proper reference voltage is applied to the differential amplifier B6. Meanwhile, "0" means programming and "1" means erasing.
Next, in the program verify, since the read bar signal line #R becomes "H", a reference transistor gate line XR is provided with a low voltage defined by the ratio of transistor TG0 and pull-down side TG1 etc. Therefore, the reference transistor TR has low current drive power because of having a lower gate voltage than the memory cell transistor TC00. So, input IN2 becomes a value nearer to the voltage when reading out "0" than the above intermediate voltage between when IN1 is reading "1" and when IN1 is reading out "0". Thus, a standard to judge data programmed as "0" becomes severe, whereby it is intended to ensure that a sufficient programming is conducted.
However, in the above conventional non-volatile semiconductor storage device, the threshold voltage of the reference transistor TR is not built in accurately in the fabrication process, and in the program verify, the voltage of the reference transistor gate line XR is determined by many elements like the transistors TR0, TG1 etc. Also, since even in the verifying, the dummy load transistors TL1 and TL2 remain connected in parallel, its resistance is a half of the load transistor TL0. Further, in the verifying, the value of reference current is also small. Therefore, as shown in FIG. 2 transcribed from FIG. 2 of Japanese patent application laid-open No. 5-36288 (1993), it operates in a region where the slope of current versus voltage curve for reference transistor TR is gentle, and has a large dispersion of operating point. Because of this, there is a problem that the judging condition in the program verifying is rougher than that in the reading and lacks in fineness.
This problem may be not material to a general EEPROM whose erasing is conducted with the support of ultraviolet rays. However, in flash EEPROM that has been used rapidly in the portable-use field with the recent popularization of personal computer and portable telephone, it is serious. Namely, the erasing of flash EEPROM is conducted by only an electrical means without the support of ultraviolet rays, and therefore a device structure suitable for that needs to be employed. So, the dispersion of erasing increases and there occurs an uneveness in erasing, which is not seen in the ultraviolet-ray erasing. Therefore, it is necessary to conduct the program verify finely. Also, adding to the erase verify, the over-erase verify also needs to be conducted.